© 2017 Shimon Schocken and Noam Nisan

Chip Name

Description

DFF

Chip Name

Bit

Chip Name

Register

Chip Name

RAM8

Chip Name

RAM64

Chip Name

RAM512

Chip Name

RAM4K

Chip Name

RAM16K

Chip Name

Data Flip-Flop (primitive)

Description

1-bit register

Description

16-bit register

Description

16-bit / 8-register memory

Description

16-bit / 64-register memory

Description

16-bit / 512-register memory

Description

16-bit / 4096-register memory

Description

16-bit / 16384-register memory

Description

PC

Chip Name

16-bit program counter

Description

Test Scripts

Compare File

Test Scripts

Compare File

Bit.tst

Test Scripts

Register.tst

Test Scripts

RAM8.tst

Test Scripts

RAM64.tst

Test Scripts

Register.cmp

Compare File

RAM8.cmp

Compare File

RAM64.cmp

Compare File

RAM512.tst

Test Scripts

RAM4K.tst

Test Scripts

RAM16K.tst

Test Scripts

RAM512.cmp

Compare File

RAM4K.cmp

Compare File

RAM16K.cmp

Compare File

PC.tst

Test Scripts

PC.cmp

Compare File

Bit.cmp

Compare File

When loaded into the supplied Hardware Simulator, your chip design (modified .hdl program), tested on the supplied .tst script, should produce the outputs listed in the supplied .cmp file. If that is not the case, the simulator will let you know. This contract must be satisfied for each chip listed above, except for the DFF chip, which is considered primitive, and thus there is no need to implement it.

The relevant reading for this project is Chapter 3 and Appendix A. Specifically, all the chips described in Chapter 3 should be implemented in the Hardware Description Language (HDL) specified in Appendix A.

For each chip, we supply a skeletal .hdl file with a missing implementation part. In addition, for each chip we supply a .tst script that instructs the hardware simulator how to test it, and a .cmp ("compare file") containing the correct output that this test should generate. Your job is to complete and test the supplied skeletal .hdl files.

The resources that you need for this project are the supplied Hardware Simulator and the files listed above. If you've downloaded the Nand2Tstris Software Suite, these files are stored in your projects/03 directory. The directory is further partitioned into two sub-directories, for reasons described below.

The Data Flip-Flop (DFF) gate is considered primitive and thus there is no need to build it: when the simulator encounters a DFF chip part in an HDL program, it automatically invokes the built-in nand2tetris/tools/builtInChips/DFF.hdl implementation.

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Built-in chips: When constructing RAM chips from lower-level RAM chip-parts, we recommend using built-in versions of the latter. Otherwise, the simulator will recursively generate numerous memory-resident software objects, one for each one of the many chip parts that make up a typical RAM unit. This may cause the simulator to run slowly, or, worse, out of memory. i.e. out of the memory of the computer on which the simulator is running. 

To avert this problem, we've partitioned the RAM chips that you have to build in this project into two sub-directories, named projects/03/a and projects/03/b. This partition is superficial, and is done with one purpose only: when building the chips stored in b, the simulator is forced to use built-in implementations of the lower-level chip parts whose .hdl programs are stored in a but not in b.

All the chips mentioned projects 0-5 can be implemented and tested using the supplied Hardware Simulator. Here is a screen shot of testing a built-in RAM8.hdl chip implementation on the Hardware Simulator: